Evolution of the semiconductor manufacturing industry is placing ever greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions are shrinking while wafer size is increasing. Economics is driving the industry to decrease the time for achieving high-yield, high-value production. Thus, minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for the semiconductor manufacturer.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Prior to being separated into individual semiconductor devices, an entire wafer of semiconductor devices may be prepared for packaging. Packaging may include coupling a chip carrier such as a substrate to a semiconductor device. Preparing a wafer of semiconductor devices for packaging may include forming structures on a surface of the semiconductor devices that may be used to couple a semiconductor device to a chip carrier. For example, relatively small solder balls may be arranged in an area on a semiconductor device. Such relatively small solder balls may be commonly referred to as “bumps,” and a wafer on which such solder balls are formed may be commonly referred to as a “bumped wafer.” The bumps may be, for example, half sphere or rectangular. The bumps may be configured to physically attach the semiconductor device to a chip carrier and to make electrical connection to a chip carrier. For example, a device may be placed on a substrate, and the solder balls may contact and melt onto an array of metal pads on the substrate. Such a packaging method may be commonly referred to as face-down bonding, flip-chip bonding, or controlled collapse chip connections (“C4”).
A chip can contain a large number of bumps. The bumps should be the same height to connect them to the board at the same time. However, bumps generally vary in height due to differences in the manufacturing process.
Bumps that are incorrectly formed on a wafer, such as those outside a height tolerance, may cause significant problems during processing, such as probing of the wafer and during use of the device. For example, incorrectly formed bumps may damage probes on a probe card thereby causing tester downtime and incurring tester repair costs. Incorrectly formed bumps may also bridge power and ground contacts thereby resulting in excessive current draw through a probe card. Therefore, bumped wafers may typically be inspected and measured prior to probing. In addition, incorrectly formed bumps may not be detected during probing and may increase the potential for failure of a packaged device. Furthermore, probing may damage bumps especially on a wafer having a relatively high number of bumps per unit area that may require high vertical forces during testing to seat probes for proper contact. In this manner, inspection and metrology of a bumped wafer may also be performed after wafer probing.
Currently available methods for three-dimensional inspection and metrology of bumped wafers generally include first acquiring data in the x-y plane and then acquiring data in the z plane. Essentially, such systems may be described as being serial in data acquisition (i.e., two-dimensional (“2D”) data acquisition followed by three-dimensional (“3D”) data acquisition). For bumped wafers, 2D defects may include, for example, missing bumps, improperly located bumps, bridged bumps, large-diameter bumps, and small-diameter bumps. Examples of 3D defects may include, but are not limited to, bumps that may be too tall or too short or that may have protruding vertical spikes or recessed vertical pits. Because currently available methods are generally not capable of simultaneous 2D and 3D data acquisition, such methods may be significantly slower than either 2D or 3D data acquisition. In addition, 3D data acquisition may be significantly slower than 2D data acquisition thereby resulting in substantially reduced sampling for 3D in comparison to sampling for 2D. As used herein, the term “sampling” may generally refer to the number of points or locations inspected or measured on a single specimen during a process. In other words, if a relatively large percentage of a wafer may be scanned to acquire x-y data, then only a much smaller percentage of the wafer may be scanned to acquire additional z data.
There are several disadvantages to currently available systems and methods for three-dimensional inspection of bumped wafers. For example, as described above, such systems may be configured to scan a wafer more than once in series to acquire 2D and 3D data for inspection and metrology. In addition, configuration of such systems may be incompatible with rapid scanning of relatively large areas of bumped wafers. Such disadvantages will generally lower a throughput of an inspection and metrology system. Furthermore, such systems may be relatively complex due to the use of separate 2D and 3D data acquisition and processing systems. This disadvantage will generally increase cost and reduce reliability of an inspection and metrology system.
Therefore, improved systems and techniques for height measurement are needed.